The present invention relates generally to integrated circuit designs, and more particularly to a static random access memory (SRAM) devices with enhanced read/write operations.
SRAM is a type of memory that is able to store data without constantly refreshing them as long as it is supplied with power. FIG. 1 schematically illustrates a circuit diagram 100 of a standard six-transistor SRAM cell with two cross-coupled inverters 102 and 104. The inverter 102 includes a pull-up transistor 114 and a pull-down transistor 116. The inverter 104 includes a pull-up transistor 118 and a pull-down transistor 120. A first storage node 106 of the inverter 102 is directly connected to the gates of both transistors of the inverter 104. A second storage node 108 of the inverter 104 is directly connected to the gates of both transistors of the inverter 102. The first storage node 106 of the inverter 102 is written to and read from through a pass gate transistor 110 that is coupled to a bit line BL. The second storage node 108 of the inverter 104 is written to and read from through a pass gate transistor 112 that is coupled to a complementary bit line BLB. The two pass gate transistors 110 and 112 are controlled by a common word line WL.
When the first storage node 106 is at a high voltage state and the pass gate transistors 110 and 112 are turned off, the pull-up transistor 118 is turned off and the pull-down transistor 120 is turned on, thereby pulling the voltage at the second storage node 108 to ground Vss. This low voltage state at the second storage node 108 turns on the pull-up transistor 114 and turns off the pull-down transistor 116, thereby sustaining the first storage node 106 with a high voltage from the voltage supply Vcc. During read operation, the word line WL is asserted to turn on the pass gate transistors 110 and 112, so that the logic states at the storage nodes 106 and 108 can be read by detecting the voltages on the bit line BL and the complementary bit line BLB. During write operation, the word line WL is asserted to turn on the pass gate transistors 110 and 112, and the bit line BL and the complementary bit line BLB are provided with programming voltages, so that the voltage states at the storage nodes 106 and 108 can be programmed.
FIG. 2 illustrates a layout view 200 of the M2 metallization level of the SRAM cell 100 shown in FIG. 1. A power line Vcc is disposed between a bit line BL and a complementary bit line BLB. The power line Vcc, bit line BL, and complementary bit line BLB are connected to higher level interconnections of the SRAM cell though various via contacts 202 and landing pads 204. The bit line BL and the complementary bit line BLB are locally constructed to connect a column of memory cells, and need to be connected to a global bit line GBL and a global complementary global bit line GBLB (not shown in the figure) on a higher level, such as the M4 metallization level, such that the cells can be accessed from outside of a memory chip.
One drawback of the conventional SRAM device is that the discharge of the bit line BL and the complementary bit line BLB through the global bit line GBL and the global complementary bit line GBLB may be delayed due the RC effect induced by the distant interconnection routes between the M2 and M4 metallization levels. As a result, the performance of the conventional SRAM device is less than ideal, which provides room for further performance improvement.